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<h1>License</h1>

<p>Unless explicitly stated otherwise, the entire contents of this book ("FPGA
Design Elements") falls under the <a href="https://opensource.org/licenses/MIT">MIT License</a>:</p>

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<p>Copyright (c) 2019-2024 Charles Eric LaForest, PhD.</p>

<p>Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:</p>

<p>The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.<p>

<p>THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.</p>
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<p>Hopefully, this license should be straightforward to get past your manager or legal team.

<h1>Disclaimer</h1>

<p>It's simply not possible for a single person to write and test and
exhaustively verify all the code in this book, and still get anything done.
Thus, the state of the code and guidelines in this book ranges from "it should
work, in theory" to "actively used in commercial applications".
<em><b>Use at your own risk.</b></em></p>

<p>That said, each design element is rather small and easy to manually inspect,
<a href="./index.html#tools">and checked with a few basic tools</a>. The
Verilog source is run through the Verilator and Icarus Verilog linters to find
mistakes, and then through the Intel Quartus Prime CAD tool to find any
elaboration and synthesis issues.  Some more complex designs are further
simulated using either Verilator or Icarus Verilog</p>

<p>If you do find any bugs, please accept my apologies, and 
<a href="mailto:eric@fpgacpu.ca?subject=FPGA%20Design%20Elements">do let me know</a> so I can fix them. (Or better
yet, please share your fix so I can include it here.) </p>

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